Using separate lithography steps in the formation of the emitter, extrinsic base or base metal, and base contact requires that all these features be controlled precisely to assure that the alignment between these features is acceptable. In order to maintain acceptable alignment, considerable investment must be made in semiconductor processing equipment and/or the alignment tolerance must be increased. Any needed increase in alignment tolerance results in larger transistor features sizes, and degrades some element of the transistor performance.
Separate process steps used in the formation of the emitter, extrinsic base or base metal, and base contacts also requires several additional lithography and deposition steps. This adds both time and money to already expensive, high performance process technologies. Additional process steps also increase the net yield loss of a given process technology.
The following describes two prior art methods for the formation of base contacts.
I. Aligned Base Post
This method uses a lithography step to define the location of a metallic post directly on the extrinsic base or base metal and align the metallic post to the emitter. The post location is then metalized to create a free-standing metallic pillar or post that will make electrical contact between the extrinsic base or base metal and the first global level of interconnect. This method is common for InP and GaAs heterojunction bipolar transistor (HBT) process technologies.
The disadvantages of this method include the following.
A. The need for a separate lithography step to form the base contact requires a critical alignment between the emitter and base contact. The failure of the critical alignment may result improper electrical contact from the first global interconnect level and the extrinsic base or base metal; electrical shorts between the transistor base and collector; and other yield loss mechanisms.
B. The need for a base post of dimensions greater than the emitter geometry to minimize yield loss. The base post height is equal to the difference between the emitter and base metal top surfaces which is larger than the emitter metal height. By definition, the post must be of a larger geometric size than the emitter.
C. The need to maintain a large extrinsic base or base metal contact area for the already large post. This results in higher than desired parasitic capacitance and degraded transistor performance.
The need for separate lithography and processing steps to form the base contact increases processing time, complexity, and cost. For example, aligned base post formation may require 2-5 business days.
II. Aligned Base Via
This method uses a lithography step to define the location of a metallic via on the extrinsic base or base metal and align the metallic via to the emitter. The via location is then etched and metalized to create an electrical contact from the first global interconnect level through the first planarizing or passivating dielectric to the extrinsic base or base metal. This method is used by some InP and GaAs HBT process and is common for Si BJT and SiGe HBT process technologies. IBM has used this method to form base contacts for silicon bipolar junction transistor (BJT) and SiGe HBT process technologies.
The disadvantages of this method include the following.
A. The need for a separate lithography step to form the base via requires a critical alignment between the emitter and base contact. The failure of the critical alignment may result improper electrical contact from the first global interconnect level and the extrinsic base or base metal; electrical shorts between the transistor base and collector; electrical shorts between the base and emitter; and other yield loss mechanisms.
B. The need for a base via of dimensions greater than the emitter geometry to minimize yield loss. The base via depth is equal to the difference between the emitter and base metal top surfaces which is larger than the emitter metal height. By definition, the via must be of a larger geometric size than the emitter. Any via corner rounding resulting from poor lithography or etch only further exacerbates this problem.
C. The need to maintain a large extrinsic base or base metal contact area for the already large via. This results in higher than desired parasitic capacitance and degraded transistor performance.
D. The need for separate lithography and processing steps to form the base contact increases processing time, complexity, and cost.
Both prior art methods of base contact formation involve a critical alignment, increased processing time, increased equipment investment costs, and increased processing costs. What is needed is a method of forming a self aligned base contact that requires substantially less critical alignment, less processing time, less equipment investment costs, and less processing costs. Also needed is a method for forming self aligned base contacts that improves processing yield. The embodiments of the present disclosure answer these and other needs.